Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

An Intelligent Fuse-box for use with Renewable Energy Sources integrated within a Domestic Environment

This paper outlines a proposal for an intelligent fuse-box that can replace existing fuse-boxes in a domestic context such that a number of renewable energy sources can easily be integrated into the domestic power supply network, without the necessity for complex islanding and network protection. The approach allows intelligent control of both the generation of power and its supply to single or groups of electrical appliances. Energy storage can be implemented in such a scheme to even out the power supplied and simplify the control scheme required, and environmental monitoring and load analysis can help in automatically controlling the supply and demand profiles for optimum electrical and economic efficiency. Simulations of typical scenarios are carried out to illustrate the concept in operation

Open Cortex-M0™ Modular Debug Unit

The debug unit of a modern digital system on chip (SoC) is a critical unit that allows users to monitor and analyze the chip’s activity that occurs throughout a SoC design. Selection of the debug unit’s correct feature set and architecture are critical to the success of the design. Debugging systems that exist have different architectures and are closely coupled to their host SoCs. As a consequence they are resource intensive to improve on due to the different nature of each SoC designs. Moreover, the bus protocols that allow the debug unit to interact with the SoC design are often designed towards the SoC design itself and are not easily extensible. This project serves to analyze existing debug units in the public domain and classify their feature sets, architectures, speed and size vs. the developed modular debug unit. Hardware description languages now enable new forms of modular designs which allow the possibility of building a modular debugging core. This allows for integration with arbitrary on chip bus systems and actual CPU processor cores. A hierarchical finite state machine (HFSM) design approach also enables the debug unit to be extended with debugging features. The size and speed of synthesized designs targeting field programmable gate array (FPGA) technology are compared, and preliminary results show that the a modular design approach debug unit is able to significantly reduce development time and be extended with new features. Future work will be carried out to build on preliminary results obtained from a modular debug unit

Investigation into the uniqueness of neonate transient otoacoustic emissions

This work presents initial findings from an investigation into the use of otoacoustic emissions (OAEs) for identifying individuals.A data set of 2009 neonate transient otoacoustic emissions was quantified for uniqueness using the Euclidean distance separation of the power spectra. Each sample was compared to all the others and the minimum separation recorded. The percentage separation for 50%, 95%, and 99% of the sample set was calculated and the distribution of the minimum separation plotted. The minimum separation between samples was 1.84% while 99% of the samples had a separation of 3.68%.A simple technique was able to achieve a separation of 3.68% for 99% of the data set, indicating it is highly likely that otoacoustic emissions are unique to an individual and of potential use as a biometric variable in an identification system

The human auditory system as a biometric

This thesis describes the utilisation of a little-known physiological phenomena (otoacoustic emissions) as a biometric. The role of the human auditory system as the sound to nerve impulse transducer is well known and extensively studied.  Less well known is the fact that this system can also generate sounds; these are called otoacoustic emissions.  Several distinct types of emission are known: of these, one particular type, transient otoacoustic emissions (TEOAEs) show potential as a biometric.  TEOAEs are sounds recorded in the ear canal as the product of an active process in the inner ear which was stimulated. Otoacoustic emissions are analysed from the perspective of what constitutes the fundamental properties a characteristic must posses to be a good biometric and the underlying mathematics are described.  Transient OAEs (TEOAEs) are evaluated against these criteria and using linear analysis demonstrate a predicted equal error rate (EER) of 0.182% with a dataset of 561 subjects, confirmed by a similar result on a smaller test dataset of 23 individuals.  Permanence of 6 months is demonstrated (with difficulty due to the nature of the current OAE acquisition systems) however stability over several years is suggested by examples from medical literature. A novel acquisition method has been developed with a view to solving the two main problems with current TEOAE acquisition systems: The acceptability problem of having to insert a probe into the ear canal (which is perceived as unnatural and unhygienic) and the extreme sensitivity of the TEOAE to the fit of the probe in the ear canal. Finally a survey of biometrics places TEOAE in context within the field.</p

The Superchip: Innovative Teaching of IC Design and Manufacture

In this paper we describe how through intelligent chip architecture, a large cohort (~100 students) of undergraduates can be given effective practical insight into IC design by designing and manufacturing their own individual ICs. To achieve this, the “Superchip” has been developed, which allows (without excessive cost in terms of time or resources) multiple student designs to be fabricated on a single IC, and encapsulated in a standard package. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. The paper provides details of the chip architecture, test regime, test vectors, and an example design

IC Design and Manufacture for Undergraduates: Theory, Design and Practice

In this paper we describe how the practical design and manufacture of modern CMOS integrated circuits (ICs) have been incorporated into the second year of our undergraduate Electronics degree program. While many undergraduate degree programs offer theoretical and design of ICs, none have published a complete design cycle teaching approach including practical manufacture and test of ICs. We demonstrate how the design process has been tightly coupled with theoretical aspects of the degree course and incorporate transferable skills into the design exercise. We will also provide the technical information on how this design exercise can be accomplished sensibly for a large cohort of students (~100) in practical terms

Innovative Teaching of IC Design and Manufacture Using the Superchip Platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

The biometric potential of transient otoacoustic emissions

Whilst the hearing capabilities of the ear are well known and extensively studied, less well known is the fact that the ear can produce sounds. These faint sounds are called otoacoustic emissions and are an involuntary feature of the biomechanical system employed to hear low amplitude sounds. Several distinct types of emission are known; of these, one particular type, transient otoacoustic emissions (TEOAEs), shows potential as a biometric. This paper graphically presents examples of TEOAEs to demonstrate the specificity of TEOAEs to an individual and their stability over a six month period of time. Several large datasets (760 and 561 subjects) and a smaller dataset are numerically analysed to classify individuals and quantify permanence over six months. It was discovered that a high level of classification performance can be obtained using the raw time-pressure data without transformation